Designing with Versal ACAP

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Course Description

This online, live, instructor-led program provides an overview of the hard block capabilities for the Versal ACAP. The focus is on:

• Describe the Versal ACAP architecture at a high level
• Describe the various engines in the Versal ACP device
• Use the various blocks from the Versal architecture to create complex systems

This course combines lectures with lab exercises to reinforce the concepts.

Pre-requisites:

• Comfort with the C/C++ programming language
• Vitis IDE software development flow
• Hardware development flow with the Vivado Design Suite
• Basic knowledge of UltraScale/UltraScale+ FPGAs and Zynq UltraScale+ MPSoCs

Course duration:

• 3 days (9 hours - 3 hours per day)

What do I gain?

• Understand the architecture of the new Versal ACAP
• Identify typical applications of Versal ACAP
• Booting and its concepts
• Versal ACAP and Vitis flow

Download PDF for course content and registration process

Register for future batch REGISTER