Designing with SystemVerilog (Self-paced Video course)
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Course Description
This self-paced course introduces the SystemVerilog language and its enhancements over Verilog, viz., data types, structures, arrays, procedural blocks, enhanced procedural constructs, reusable tasks and packages. The program comes with insightful theory lectures, lab code and lab demos.
Pre-requisites:
- Verilog knowledge
Access:
- Login and password will be shared within 1 business day after payment and registration
- Content will be made available for 1 month from start of access
What do I gain?
- Describe the benefits and features of SystemVerilog for RTL design
- Identify the new data types supported in SystemVerilog
- Use an enumerated data type
- Explain how to use arrays, structures and unions for RTL coding
- Describe the new procedural blocks and their effect on Synthesis
- Define the ability to reuse tasks and packages
Download PDF for course content and registration process
Need More Info ?
Contact us: 
(For Students)
+91-9844182555(For Corporates)
+91-8754722266
Email us: training@coreel.com
Admission Office:
(080) 4197 0445
Front Office:
(080) 4197 0400