Course Description
This workshop illustrates the different approaches for efficiently migrating existing designs to the AMD Versal adaptive SoC from AMD UltraScale+ devices. The course covers design migration considerations for different system design types. The emphasis is on:
- Identifying and comparing various functional blocks in the Versal Adaptive SoC to those in previous-generation UltraScale+ devices
- Reviewing the approaches for migrating existing designs to the Versal Adaptive SoC
- Describing the development platforms for all developers
- Enabling top-level RTL flows for Versal devices
- Identifying design migration considerations for PL-only designs and Zynq™ UltraScale+ MPSoC designs
This course combines lectures with lab demos to reinforce concepts.
Pre-requisites:
- Familiarity with designing UltraScale+ FPGAs and adaptive SoCs
- Familiarity with the AMD Vivado and Vitis tools
Course duration:
Agenda
- AMD Versal Overview
- AMD Versal Design Tool Flow
- Programmable Logic Design Migration Considerations
- Identifying and comparing various functional blocks in the Versal adaptive SoC to those in previous-generation UltraScale+ devices
- Reviewing the approaches for migrating existing designs to the Versal adaptive SoC
- Identifying design migration considerations for PL-only designs and Zynq UltraScale+ MPSoC designs
- Migrating Zynq UltraScale+ MPSoC-based system-level designs to the Versal adaptive SoC
- Detailing Versal device hardware debug features