Online Internship on Functional Verification using SystemVerilog

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Course Description

Sandeepani offers 1 month Vacation Internship Program for students currently doing their B.E/B.Tech, M.E./M.Tech in Electronics/ Instrumentation/Electrical/ Telecommunication. This program is specifically designed introduce participants to functional verification using the SystemVerilog HVL. The participants will get an opportunity to work on a project during the course.

This course combines lectures with lab exercises to reinforce the concepts.

Program Highlights:

• 24-hour access to Mentor Graphics licenses
• Conceptual training on topics outside regular university curriculum
• Hands-on labs using industry standard EDA tools from Mentor Graphics

Who can attend:

• Students pursuing their UG/PG/Research
• Faculty members keen on learning Design Verification using SystemVerilog
• Working professionals interested in skill development

Course duration:

• 1 month (1 hour per day)

What do I gain?

• Describe the advantages and enhancements to SystemVerilog to support verification
• Define the new data types available in SystemVerilog
• Analyze and use the improvements to tasks and functions
• Discuss and use the various new verification building blocks available in SystemVerilog
• Describe object-oriented programming and create a class-based verification environment
• Explain the various methods for creating random data
• Create and utilize random data for generating stimulus to a DUT
• Identify how SystemVerilog enhances functional coverage for simulation verification
• Utilize assertions to quickly identify correct behavior in simulation

Download PDF for course content and registration process

Register for future batch REGISTER