Online Internship on RTL2GDSII - ASIC Physical Design and Verification

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Course Description

Sandeepani offers 1 month Online Internship Program for students currently doing their B.E/B.Tech,M.E./M.Tech in Electronics/Instrumentation/Electrical/Telecommunication. This program is designed to introduce participants to the semi-custom RTL to GDSII flow in ASIC Physical Design. The participants will get an opportunity to work on a project during the course.

This course combines lectures with lab exercises to reinforce the concepts.

Who can attend:

• Students pursuing their UG/PG/Research

Pre-requisities:

• Basic understanding of Digital Circuits and Verilog

Course duration:

• 1 month (1 hour per day)

What do I gain?

• Understand the Semi-custom ASIC Physical Design flow from RTL to GDSII
• Learn about the inputs required for synthesis and different synthesis techniques
• Understand the relevance of Clock Tree Synthesis and Static Timing Analysis
• Learn Place and Route techniques
• Apply physical verification rules like DRC and LVS

Download PDF for course content and registration process

Register for future batch REGISTER