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Course Description
This online, live, instructor-led Internship program provides an Introduction to ASIC Design and Verification Environment. It addresses the full custom design flow strategies to verify designs using Industry standard Mentor Graphics EDA tools. Some of the topics addressed include Design challenges & Optimization techniques in transistor model, various Analyses on transistor model like transient, DC and AC analysis, Post Layout simulation environment, issues of Place and Route in full custom designs and Physical Verification strategies using signoff Calibre tool for various Layout checks - DRC, LVS and PEX rule files.
This course combines lectures with lab exercises to reinforce the concepts.
Who can attend:
Pre-requisities:
Course duration:
What do I gain?
Contact us:
(For Students)
+91-9844182555
(For Corporates)
+91-8754722266
Email us: training@coreel.com
Admission Office:
(080) 4197 0445
Front Office:
(080) 4197 0400