Accelerating Applications with the Vitis Unified Software Environment

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Course Description

In this interactive online workshop, you will learn how to develop, debug, and profile new or existing C/C++ and RTL applications in the Vitis unified software environment targeting both data center (DC) and embedded applications. The emphasis of this course is on:

• Building a software application using the OpenCL API and the Linux-based Xilinx runtime (XRT) to schedule the hardware kernels and control data movement on an embedded processor platform
• Demonstrating the Vitis environment GUI flow and makefile flow for embedded applications
• Describing the Vitis platform execution model and XRT
• Describing kernel development using C/C++ and RTL
• Utilizing the Vitis analyzer tool to analyze reports
• Explaining the design methodology to optimize a design

This course combines lectures with lab exercises to reinforce the concepts.

Pre-requisites:

• Basic knowledge of Xilinx FPGA architecture
• Comfort with the C/C++ programming language
• Software development flow

Course duration:

• 3 days (9 hours - 3 hours per day)

What do I gain?

• Describe how the FPGA architecture lends itself to parallel computing
• Explain how the Vitis unified software environment helps software developers to focus on applications
• Describe the Vitis (OpenCL API) execution model
• Analyze the OpenCL API memory model
• Create kernels from C, C++, or RTL IP using the RTL Kernel Wizard
• Apply host code optimization and kernel optimization techniques
• Move data efficiently between kernel and global memory
• Profile the design using the Vitis analyzer tool

Download PDF for course content and registration process

Register for future batch REGISTER