Ultrafast Design Methodology

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Course Description

This online, live, instructor-led program describes ultrafast design methodology checklist. The course describes the FPGA design best practices and skills to be successful using the Vivado Design Suite. This includes the necessary skills to improve design speed and reliability, including: system reset design, synchronization circuits, optimum HDL coding techniques, and timing closure techniques using the Vivado software. This course encapsulates this information with Ultrafast design methodology case studies. The course combines lectures with lab exercises to reinforce the concepts.

This course combines lectures with lab exercises to reinforce the concepts.

Pre-requisites:

• Basic HDL Knowledge (Verilog or VHDL)

Course duration:

• 3 days (9 hours - 3 hours per day)

What do I gain?

• Optimize HDL code to maximize the FPGA resources
• Define a properly constrained design
• Project based and Non Project batch scripting
• Essential Tcl Scripting for the Vivado Design Suite
• Synchronous design techniques
• Handling multiple clocks
• Timing closure techniques and Last mile strategies

Download PDF for course content and registration process

Register for future batch REGISTER