Static Timing Analysis and Clock Domain Crossing

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3. Static Timing Analysis and Clock Domain Crossing (Self-paced Video course)

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Course Description

This self-paced course helps participants to review the underlying database and static timing analysis (STA) mechanisms. The emphasis is on utilizing project based scripting flow for navigating the design, creating Xilinx design constraints and analyzing timing reports. The course focuses on creating path specific constraints, false paths, max and min delay constraints and priority of the timing exceptions in the Vivado timing engine. The course also addresses on various synthesis and implementation techniques for achieving better timing closure. It also covers a section on Clock Domain Crossing and how to constrain a design with multiple clock sources.

Pre-requisites:

• Knowledge of digital circuits
• Basic HDL Knowledge (Verilog or VHDL)

Access:

• Login and password will be shared within 1 business day after payment and registration
• Content will be made available for 1 month from start of access

What do I gain?

• Create appropriate clock, input and output delay constraints
• Analyze different timing reports
• Define a properly constrained design
• Describe setup and hold checks
• Identify key areas to optimize the design to meet performance goals and objectives
• Synthesis Techniques- Pipelining and Resource Sharing
• Timing Exceptions
• Implementation Techniques- Incremental compile and Physical optimization
• Congestion and Floorplanning
• Clock Domain Crossing

Download PDF for course content and registration process

Register for Online On-demand batch REGISTER
Register an enquiry ENQUIRY