Zynq UltraScale+ MPSoC for the Hardware Designer

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Course Description

This course provides hardware designers with an overview of thecapabilities and support for the Zynq UltraScale+ MPSoC family from a hardware architectural perspective. The emphasis is on:

• Identifying the key elements of the application processing unit (APU) and real-time processing unit (RPU)
• Reviewing the various power domains and their control structure
• Illustrating the processing system (PS) and programmable logic (PL) connectivity
• Utilizing QEMU to emulate hardware behavior

This course combines lectures with lab exercises to reinforce the concepts.

Pre-requisites:

• Suggested: Understanding of the Zynq-7000 architecture
• Basic familiarity with embedded software development using C (to support testing of specific architectural elements)

Course duration:

• 3 days (9 hours - 3 hours per day)

What do I gain?

• Enumerate the key elements of the application processing unit (APU) and real-time processing unit (RPU)
• List the various power domains and how they are controlled
• Describe the connectivity between the processing system (PS) and programmable logic (PL)
• Utilize QEMU to emulate hardware behavior

Download PDF for course content and registration process

Register for future batch REGISTER