Physical Design and Verification RTL to GDSII

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Course Description

This program is designed to introduce participants to the semi-custom RTL to GDSII flow in ASIC Physical Design. The participants will get an opportunity to work on a project during the course.

This course combines lectures with lab exercises to reinforce the concepts.

Who can attend:

• Faculty, research scholars and post graduate students interested in gaining knowledge in the RTL to GDSII ASIC Design and Verification flow

Course duration:

• 3 days (9 hours - 3 hours per day)

What do I gain?

• Understand the Semi-custom ASIC Physical Design flow from RTL to GDSII
• Learn about the inputs required for synthesis and different synthesis techniques
• Understand the relevance of Clock Tree Synthesis and Static Timing Analysis
• Learn Place and Route techniques
• Apply physical verification rules like DRC and LVS

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