Designing with Verilog (Self-paced Video course)

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Course Description

This self-paced course provides a thorough introduction to the Verilog language. The program comes with insightful theory lectures, lab code and lab demos. The emphasis is on employing structural, register transfer level (RTL), and behavioral coding styles in Verilog. It also delves into writing testbenches for design verification.

This course combines lectures with lab exercises to reinforce the concepts.

Pre-requisites:

• Knowledge of digital circuits

Access:

• Login and password will be shared within 1 business day after payment and registration
• Content will be made available for 1 month from start of access

What do I gain?

• Introduce Verilog as a Hardware Description Language
• Identify the differences between data flow, behavioral and structural coding styles
• Use concurrent and sequential control structure to regulate information flow
• Simulate a basic Verilog design
• Write a Verilog testbench and identify simulation-only constructs
• Modeling FSMs - Mealy and Moore
• Learn to implement functions and tasks to optimize writing RTL and testbench

Download PDF for course content and registration process

Register for Online On-demand batch REGISTER
Register an enquiry ENQUIRY