Designing with the UltraScale and UltraScale+ Architectures

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Course Description

This live, online, interactive course introduces the UltraScale and UltraScale+ architectures to both new and experienced designers. The emphasis is on:

• Introducing CLB resources, clock management resources (MMCM and PLL), global and regional clocking resources, memory and DSP resources, and source-synchronous resources
• Describing improvements to the dedicated transceivers and Transceiver Wizard
• Migrating existing designs and IP to the UltraScale architecture with optimal use of the Vivado Design Suite

This course combines lectures with lab exercises to reinforce the concepts.

Pre-requisites:

• Designing FPGAs Using the Vivado Design Suite 1 course
• Intermediate VHDL or Verilog knowledge

Course duration:

• 2 days (6 hours - 3 hours per day)

What do I gain?

• Take advantage of the primary UltraScale architecture resources
• Describe the new CLB capabilities and the impact that they make on your HDL coding style
• Define the block RAM, FIFO, and DSP resources available
• Describe the new type of memory structures available in UltraScale+ devices, such as UltraRAM and the high bandwidth memory (HBM) available in Virtex UltraScale+ devices
• Properly design for the I/O and SERDES resources
• Identify the MMCM, PLL, and clock routing resources included
• Identify the hard IP resources available for implementing high-performance DDR4 memory interfaces
• Describe the additional features of the dedicated transceivers
• Effectively migrate your IP and design to the UltraScale architecture as quickly as possible

Download PDF for course content and registration process

Register for 24 May 2021 Online batch REGISTER
Register for future batch REGISTER