Physical Design and Verification RTL to GDSII

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Course Description

This online, live, instructor-led program provides participants with a hands-on experience with Design for Testability (DFT) techniques and tools. With the increase in size and complexity of chips, facilitated by the advancement of manufacturing technologies, DFT has become a critical process in the SoC and ASIC Design flow, and facilitates design for detecting manufacturing defects. The live, instructor-led program comes with lectures, demos and hands-on lab to ensure quality learning.

This course combines lectures with lab exercises to reinforce the concepts.

Who can attend:

• Faculty, research scholars and post graduate students interested in gaining knowledge in DFT

Course duration:

• 3 days (9 hours - 3 hours per day)

What do I gain?

• DFT
• Scan-Chain Insertion with multiple scan chain
• Fault Model
• ATPG
• Pattern Debugging
• Test point Insertion
• Scan Chain compression
• Analyze test coverage and improvements to achieve goals with optimal patterns.
• Validate the patterns in a pre-silicon simulation environment

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