Back to: Designing with Verilog
Welcome to the Designing with Verilog course. This course is divided into 10 chapters:
1 – Introduction to Verilog
2 – Verilog Data Types
3 – Operators in Verilog
4 – Verilog Modules and Ports
5 – Data flow and Structural Modeling
6 – Behavioral Modeling
7 – Testbenches in Verilog
8 – Functions and Tasks
9 – Modeling FSMs
10 – Compiler Directives and Generate Statements
Each chapter has a theory video. Where applicable, lab files and lab video are made available chapter-wise.
Recommended software for this course:
- Mentor Graphics QuestaSim or ModelSim
- Xilinx Vivado
The course contents will be available for 1 month from start of access.
For assistance while taking up the course, email training@coreel.com
Happy Learning!