Back to: RTL Modeling with SystemVerilog
This self-paced course introduces the SystemVerilog language and its enhancements over Verilog, viz., data types, structures, arrays, procedural blocks, enhanced procedural constructs, reusable tasks and packages. The program comes with insightful theory lectures, lab code and lab demos.
Pre-requisites:
- Knowledge of digital circuits
- Basic HDL Knowledge (Verilog or VHDL)
General Instructions
Welcome to the RTL Modeling with SystemVerilog course. This course is divided into 7 chapters:
1 – Introduction to SystemVerilog
2 – Data types and operators
3 – Port Associations
4 – Procedural blocks and routines
5 – Enumerated data types
6 – Arrays, Structures, Unions and Packages
7 – SystemVerilog Interfaces
Each chapter has theory and lab videos. Where applicable, lab files are made available chapter-wise.
Recommended software for this course is Mentor Graphics QuestaSim.
The course contents will be available for 1 month from start of access.
For assistance while taking up the course, email training@coreel.com