Back to: Functional Verification using SystemVerilog
This self-paced course takes learners deeper into the SystemVerilog language and how SystemVerilog is used as a Hardware Verification Language (HVL). Some of the powerful SystemVerilog concepts covered are OOPS in SystemVerilog, Assertions, Interfaces, Ramdomization, Functional Coverage, Inter-Process Communication and the Direct Programming Interface.
Pre-requisites:
- Knowledge of digital circuits
- Working knowledge of HDL (preferably Verilog)
- Basic knowledge of SystemVerilog constructs used for design
General Instructions
Welcome to the Verification using SystemVerilog course. This course is divided into 12 chapters:
1 – Introduction to SystemVerilog
2 – SystemVerilog Data types
3 – Procedural statements
4 – SystemVerilog building blocks
5 – OOPS concepts
6 – SystemVerilog Assertions
7 –Randomization
8 – Functional coverage
9 – Inter-Process Communication
10 – Direct Programming Interface
11 – SystemVerilog Testbench
Each chapter has theory and lab videos. Where applicable, lab files are made available chapter-wise. Recommended software for this course is Mentor Graphics QuestaSim.
The course contents will be available for 1 month from start of access. For assistance while taking up the course, email training@coreel.com