Static Timing Analysis and Clock Domain Crossing

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This self-paced course helps participants to review the underlying database and static timing analysis (STA) mechanisms. The emphasis is on utilizing project based scripting flow for navigating the design, creating Xilinx design constraints and analyzing timing reports.  The course focuses on creating path specific constraints, false paths, max and min delay constraints and priority of the timing exceptions in the Vivado timing engine. The course also addresses on various synthesis and implementation techniques for achieving better timing closure. It also includes a section on Clock Domain Crossing and what constraints are to be provided in multi-clock designs.

Course Information

Difficulty: Advanced

Categories: ,

 

STA and CDC

₹5,999.00
1 month of access
 
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General Instructions

General Instructions

Introduction to STA

Introduction to STA
Lab demo – HDL Coding Techniques

STA and Clocks

STA and Clocks
Lab demo – Baselining

Synthesis Techniques

Synthesis Techniques
Lab demo – Pipelining
Lab demo – Resource Sharing
Lab demo – Register Duplication

Timing Exceptions

Timing Exceptions
Lab demo – Constraining a purely combinational logic design
Lab demo – Timing Exceptions

Implementation Techniques

Implementation Techniques
Lab demo – Incremental Compile
Lab demo – Physical Optimization
Lab demo – Floorplanning

Clock Groups

Clock Groups
Lab demo – Clock groups

Clock Domain Crossing

Clock Domain Crossing