Embedded System Design using Zynq

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This self-paced online course gives participants an in-depth view of the Embedded System Design flow using Xilinx tools and technologies. It covers the Zynq-7000 architecture, PS-PL interface, using the IP Integrator in Vivado and Software flow and Debugging using Vitis. The program comes with insightful theory lectures, lab code and lab demos.

Course Information

Difficulty: Intermediate

Categories: ,

 

Embedded System Design using Zynq

₹6,999.00
1 month of access
Enroll

General Instructions

Introduction
Lesson 1 of 1 within section General Instructions. You must enroll in this course to access course content.

Introduction to Embedded System Design

Introduction to Embedded System Design
Lesson 1 of 1 within section Introduction to Embedded System Design.

Xilinx SoC Design Flow

Overview of Embedded Hardware Development
Lesson 1 of 4 within section Xilinx SoC Design Flow. You must enroll in this course to access course content.
Overview of Embedded Software Development
Lesson 2 of 4 within section Xilinx SoC Design Flow. You must enroll in this course to access course content.
Driving the Vitis Software Development Tool
Lesson 3 of 4 within section Xilinx SoC Design Flow. You must enroll in this course to access course content.
Lab: Simple Hardware Design
Lesson 4 of 4 within section Xilinx SoC Design Flow. You must enroll in this course to access course content.

Zynq Architecture

Application Processor Unit (APU)
Lesson 1 of 3 within section Zynq Architecture. You must enroll in this course to access course content.
Input/Output Peripherals
Lesson 2 of 3 within section Zynq Architecture. You must enroll in this course to access course content.
Lab: PS-UART
Lesson 3 of 3 within section Zynq Architecture. You must enroll in this course to access course content.

PS-PL Interface

PS-PL Interface
Lesson 1 of 6 within section PS-PL Interface. You must enroll in this course to access course content.
AXI-Introduction
Lesson 2 of 6 within section PS-PL Interface. You must enroll in this course to access course content.
AXI-Variations
Lesson 3 of 6 within section PS-PL Interface. You must enroll in this course to access course content.
AXI-Trasactions
Lesson 4 of 6 within section PS-PL Interface. You must enroll in this course to access course content.
Lab 3 code
Lesson 5 of 6 within section PS-PL Interface. You must enroll in this course to access course content.
Lab 3: Adding Peripherals in Programmable Logic
Lesson 6 of 6 within section PS-PL Interface. You must enroll in this course to access course content.

IP Integrator and Packager

Designing with IP integrator
Lesson 1 of 4 within section IP Integrator and Packager. You must enroll in this course to access course content.
Creating a custom IP
Lesson 2 of 4 within section IP Integrator and Packager. You must enroll in this course to access course content.
Lab 4 code
Lesson 3 of 4 within section IP Integrator and Packager. You must enroll in this course to access course content.
Lab 4: Creating and adding your own custom IP (AXI IP)
Lesson 4 of 4 within section IP Integrator and Packager. You must enroll in this course to access course content.

Debugging the Zynq SoC

Debugging the Zynq SoC
Lesson 1 of 3 within section Debugging the Zynq SoC. You must enroll in this course to access course content.
Lab 5 code
Lesson 2 of 3 within section Debugging the Zynq SoC. You must enroll in this course to access course content.
Lab 5: Working with Timers and Debugging Applications using Vitis
Lesson 3 of 3 within section Debugging the Zynq SoC. You must enroll in this course to access course content.

Introduction to MPSoC and RFSoC architectures

Introduction to MPSoC and RFSoC architectures
Lesson 1 of 1 within section Introduction to MPSoC and RFSoC architectures. You must enroll in this course to access course content.