Designing with Verilog

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This self-paced course provides a thorough introduction to the Verilog language. The program comes with insightful theory lectures, lab code and lab demos. The emphasis is on employing structural, register transfer level (RTL), and behavioral coding styles in Verilog. It also delves into writing testbenches for design verification.

Course Information

Difficulty: Beginner

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Designing with Verilog

₹4,999.00
1 month of access
 
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General Instructions

General Instructions
Lab Manual

Introduction to Verilog

Introduction to Verilog

Verilog Data Types

Verilog Data Types
Lab demo – Project creation and simulation in Vivado
Lab demo – Simulating a sequential design

Operators in Verilog

Operators in Verilog
Lab demo – ALU design using operators

Verilog Modules and Ports

Verilog Modules and Ports

Data flow and structural modeling

Data flow and structural modeling
Lab demo – Dataflow modeling
Lab demo – Structural modeling

Behavioral Modeling

Behavioral Modeling
Lab demo – Behavioral modeling of up-counter

Testbenches in Verilog

Testbenches in Verilog
Lab demo – Testbench design and simulation

Functions and Tasks

Functions and Tasks

Modeling FSMs

Modeling FSMs
Lab demo – Sequence detector using Moore FSM

Compiler Directives and Generate Statements

Compiler Directives and Generate Statements
Lab demo – RCA using generate