Designing with Verilog

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This self-paced course provides a thorough introduction to the Verilog language. The program comes with insightful theory lectures, lab code and lab demos. The emphasis is on employing structural, register transfer level (RTL), and behavioral coding styles in Verilog. It also delves into writing testbenches for design verification.

Course Information

Difficulty: Beginner

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Designing with Verilog

₹4,999.00
1 month of access
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General Instructions

General Instructions
Lesson 1 of 2 within section General Instructions.
Lab Manual
Lesson 2 of 2 within section General Instructions. You must enroll in this course to access course content.

Introduction to Verilog

Introduction to Verilog
Lesson 1 of 1 within section Introduction to Verilog.

Verilog Data Types

Verilog Data Types
Lesson 1 of 3 within section Verilog Data Types. You must enroll in this course to access course content.
Lab demo – Project creation and simulation in Vivado
Lesson 2 of 3 within section Verilog Data Types. You must enroll in this course to access course content.
Lab demo – Simulating a sequential design
Lesson 3 of 3 within section Verilog Data Types. You must enroll in this course to access course content.

Operators in Verilog

Operators in Verilog
Lesson 1 of 2 within section Operators in Verilog. You must enroll in this course to access course content.
Lab demo – ALU design using operators
Lesson 2 of 2 within section Operators in Verilog. You must enroll in this course to access course content.

Verilog Modules and Ports

Verilog Modules and Ports
Lesson 1 of 1 within section Verilog Modules and Ports. You must enroll in this course to access course content.

Data flow and structural modeling

Data flow and structural modeling
Lesson 1 of 3 within section Data flow and structural modeling. You must enroll in this course to access course content.
Lab demo – Dataflow modeling
Lesson 2 of 3 within section Data flow and structural modeling. You must enroll in this course to access course content.
Lab demo – Structural modeling
Lesson 3 of 3 within section Data flow and structural modeling. You must enroll in this course to access course content.

Behavioral Modeling

Behavioral Modeling
Lesson 1 of 2 within section Behavioral Modeling. You must enroll in this course to access course content.
Lab demo – Behavioral modeling of up-counter
Lesson 2 of 2 within section Behavioral Modeling. You must enroll in this course to access course content.

Testbenches in Verilog

Testbenches in Verilog
Lesson 1 of 2 within section Testbenches in Verilog. You must enroll in this course to access course content.
Lab demo – Testbench design and simulation
Lesson 2 of 2 within section Testbenches in Verilog. You must enroll in this course to access course content.

Functions and Tasks

Functions and Tasks
Lesson 1 of 1 within section Functions and Tasks. You must enroll in this course to access course content.

Modeling FSMs

Modeling FSMs
Lesson 1 of 2 within section Modeling FSMs. You must enroll in this course to access course content.
Lab demo – Sequence detector using Moore FSM
Lesson 2 of 2 within section Modeling FSMs. You must enroll in this course to access course content.

Compiler Directives and Generate Statements

Compiler Directives and Generate Statements
Lesson 1 of 2 within section Compiler Directives and Generate Statements. You must enroll in this course to access course content.
Lab demo – RCA using generate
Lesson 2 of 2 within section Compiler Directives and Generate Statements. You must enroll in this course to access course content.

Memory Modeling, Types of FIFO

Implementation of RAM and ROM, Synchronous FIFO
Lesson 1 of 3 within section Memory Modeling, Types of FIFO. You must enroll in this course to access course content.
Lab: Implementation of ROM
Lesson 2 of 3 within section Memory Modeling, Types of FIFO. You must enroll in this course to access course content.
Lab: Implementation of Single port RAM and verify using File I/O based testbench
Lesson 3 of 3 within section Memory Modeling, Types of FIFO. You must enroll in this course to access course content.