This self-paced course takes learners deeper into the SystemVerilog language and how SystemVerilog is used as a Hardware Verification Language (HVL). Some of the powerful SystemVerilog concepts covered are OOPS in SystemVerilog, Assertions, Interfaces, Randomization, Functional Coverage, Inter-Process Communication and the Direct Programming Interface.
- Before starting this course you must complete the required prerequisite course: RTL Modeling with SystemVerilog
Functional Verification using SystemVerilog
₹9,999.00
1 month of access