Physical Verification using Calibre

This self-paced course provides a detailed description of the ASIC Physical Verification process. The program comes with theory lectures, lab demos and hands-on labs on a cloud environment. Some of the key concepts covered are DRC, LVS and Parasitic Extraction.

Course Information

Difficulty: Advanced

Categories: ASIC

₹5,999.00

1 month of access

General Instructions

Introduction to IC design flows

Introduction to Physical Verification

Basic DRC Concepts – Block level

Demo 1 – Block level DRC checks

Advanced DRC Concepts – Chip level

Demo 2 – Chip level DRC checks

Demo 3 – Chip level DRC checks

Hands-on Lab 1

Lab instructions 1

Lab 1 – Schematic editing using sedit

Lab 2 – Layout editing using ledit

Lab 3 – DRC checks using calibre

Introduction to LVS

LVS Text based Connectivity Checks, Soft Connection errors and Fixing Methodologies

Demo 4 – LVS Text based Connectivity Checks, Soft Connection errors and Fixing Methodologies

Demo 5 – LVS Text based Connectivity Checks, Soft Connection errors and Fixing Methodologies

LVS Shorts and Open circuit errors and Fixing Methodologies

Demo 6 – LVS Shorts and Open circuit errors and Fixing Methodologies

Demo 7 – LVS Shorts and Open circuit errors and Fixing Methodologies

Demo 8 – LVS Shorts and Open circuit errors and Fixing Methodologies

Hands-on Lab 2

Lab instructions 2

Lab 4 – LVS open circuit check

Lab 5 – LVS short circuit check

Lab 6 – LVS port name check

Lab 7 – LVS malformed device

Introduction to Parasitic Extraction and PEX Concepts

Demo 9 – Various Parasitic Models and Extraction Methods

Hands-on Lab 3

Lab instructions 3

Lab 8 – Parasitic extraction