Professional Development Course on VLSI System on a Chip Design (Full-time)

Sandeepani offers the 16-week full time (Monday – Friday, 8 hours a day) Professional Development Course for recent graduates and post-graduates in Electronics/Electrical/Telecommunication engineering. This program is specifically designed with an objective to provide a sound platform for the students and prepare them for a successful career in the fields of VLSI Design and verification with FPGAs.
The PDC offers the right blend of classroom teaching, quality hands-on training from 'concept-to-project', covering design methodology using industry standard tools and practices. The course includes a project work as well.
Placement assistance is provided to those who complete all modules of this course and a pre-placement test.

Course Duration: 16 Weeks

Course Structure and Outline

Mod.

Module Title

What You Learn

P1
(5 Days)

Engineering primer

  • Number systems
  • Logic gates
  • Boolean expressions
  • Introduction to registers and counters
  • Introduction to Embedded systems

C1
(10 Days)

Advanced Digital System Design

  • Synchronous Finite State Machine Design
  • Data-path elements – Arithmetic Structures
  • Introduction to Programmable Platforms
  • Design Capture and Simulation
  • Practical Digital System Design Examples

C2
(20 Days)

Verilog

  • Hardware Modeling Overview,
  • Verilog language concepts
  • Modules and Ports
  • Dataflow Modeling
  • Introduction to Test benches
  • Operators
  • Procedural Statements
  • Controlled Operation Statements
  • Coding for Finite State Machines
  • Coding For Synthesis
  • Tasks and Functions
  • Advanced Verilog Test benches

C3
(15  Days)

FPGA Design

  • FPGA Architecture - Basic Components of FPGA (LUT, CLB, Switch Matrix, IOB), FPGA Architecture of different families: 7-series and UltraScale devices, Zynq
  • FPGA Design Flow – Xilinx Vivado tool Flow, Reading Reports, Implementing IP cores, Debugging Using Vivado Analyzer
  • Optimal FPGA Design – HDL Coding Techniques for FPGA, FPGA Design Techniques, Synthesis Techniques, Implementation Options
  • Static Timing Analysis – Global Timing Constraints, Path specific timing constraints, Achieving Timing Closure, Introduction to Reset techniques, Clock Domain Crossing, Multiple Clock Domains

Integrated in the course

Course Project

  • Design/Implementation

Elective 1
(15 Days)

Functional Verification with SystemVerilog

  • Introduction to Verification and Verification Plan
  • Verification Tools
  • Stimulus and Response
  • SystemVerilog Basics – Introduction to SystemVerilog, Enhancement made in SystemVerilog over Verilog, Interface and Modports
  • Introduction to Bus Functional Models
  • Verification environment and its components
  • SystemVerilog for Verification - SystemVerilog Event Ordering, Clocking block and Program block, OOP's Concept of SystemVerilog - Parameterized classes, Virtual interface, Constrained Randomization techniques, Functional Coverage (Coverage Driven Verification), SystemVerilog Assertions

Elective 2
(10 Days)

UVM

  • Introduction to UVM
  • UVM Classes
  • UVM Factory
  • Sequence Item, Sequencer, Virtual Sequences
  • Transaction Level Modeling
  • UVM Reporting Methods
  • Development of Reusable Verification Environment

1) The contents listed above is a representative outline and is subject to change at short notice in compliance with the current industry demands.

2) Legend: P# - Primer Module, C# - Core Module

Download course brochure here.

Need More Info ?

Contact us : (+91) 99725 21707 and (+91) 98441 82555

Email us : training@coreel.com

Admission Office:

(080) 4197 0445

Front Office:

(080) 4197 0400