Course Description

This course introduces the AMD Versal Adaptive SoC architecture and design methodology. The emphasis is on:

• Getting a high-level overview of the AMD Versal architecture, illustrating the various engines available in the AMD Versal architecture
• Understanding the design flow to map the various engines in the AMD Versal architecture with the tools required and describes how to target them for final image assembly
• Using the various blocks from the AMD Versal architecture to create complex systems
• Knowing the reasons to use the network on chip, its basic elements, and common terminology
• Introducing the AI Engine array architecture, terminology, and AIE interfaces

This course combines lectures with lab demos to reinforce concepts.

Pre-requisites:

• Comfort with the C/C++ programming language
• Vitis IDE software development flow
• Hardware development flow with the Vivado Design Suite
• Basic knowledge of UltraScale/UltraScale+ FPGAs and Zynq UltraScale+ MPSoC

Course duration:

• 1 day (10am - 5pm)

Agenda

• Architecture and Overview
• Design Tool Flow
• Versal Programmable Logic
• Versal Processing System
• NoC Introduction and Concepts
• Versal AI Engine